In conventional semiconductor devices having a function classifying chips and conventional test methods of the semiconductor devices, classification information such as chip ID or the like and quality information on result of a test on wafer state or the like are written in a non-volatile memory portion such as a fuse after finishing wafer processes. The information are read from the non-volatile memory portion so as to be used for improvement of assembly processes or defect analysis after finishing packaging (for references, Japanese Patent Unexamined Publication (Kokai) No. H8-213464 and Japanese Patent Unexamined Publication (Kokai) No. 2004-40103).
However, a hard test cannot be performed on wafer state before packaging processes. Accordingly, a simple functional test is only carried out in conventional semiconductor devices and conventional test methods. Especially, semiconductor devices having a DRAM portion are examined by die sort test (D/S test) with harder specifications on proper test items of DRAM cell, such as pause time or access time, on wafer state. This is because a slight deviation of process parameters in wafer processes produces larger variations in DRAM performance.
In spite of the hard test, conventional semiconductor devices and conventional test methods cause lower yield of DRAM products by the variations in DRAM performance in a test with the test items after packaging processes (product test).
Furthermore, a product specification of DRAM is often classified into several kinds of the ranks, since each one of the test items has large variations in performance. Therefore, the product test is carried out by a special specification for combination of user specific requirement. Accordingly, the product test produces lower yield of or longer delivery period for shipping products.